OpenMCS
A low-cost FPGA-based multichannel scaler and dual-input pulse counter, built for laboratory time-resolved measurements.
Acquisition in hardware. Control on the desktop.
OpenMCS uses a Sipeed Tang Primer 25K FPGA Dock, a Teensy 4.0 microcontroller, and an SN74LVC245A input buffer.
The FPGA performs triggered histogram accumulation; the Teensy bridges acquisition and control to a Python desktop application for visualization, analysis, and export.
Documented capabilities
1–16,384 bins
Repeated-pass accumulation with configurable bin dwell.
30 ns minimum bin
Nominal 100 MHz acquisition clock; 300 MHz input sampling is a separate specification.
Dual-input
64-bit cumulative counters and event/trigger count-rate traces.
Zero-dead-time design
Hardware accumulation; verify system limits for each application.
Python GUI
Live previews, regions of interest, background subtraction, uncertainty and SNR.
CSV + images
Run naming, plots, verification tools, and sample data.
Specifications are taken from the public repository README; see its documentation for operating conditions, caveats, and verification evidence.